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| The Hybrid Pipelining Implementation of AES in the Feedback Mode Based on CPLD/FPGA |
| Peng Gen-peng; Liu Chang-shu; Li Zhi-hua |
| School of Electronic and Information Engineering Tianjin University Tianjin 300072 China |
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Abstract Although using pipelining structure in the hardware implementation can generally provide higher throughput, the application of this structure in current cryptography is limited, because they are not suitable for most common feedback modes. This paper puts forward a design of the hybrid pipelining architecture of AES. By including in the AES standard interleaved modes of operation, the design successfully implements the algorithm, which operates in the CBC mode. In this design, four data blocks can be dealt with in parallel (called one-encryption or one-decryption), and at the same time two encryptions or decryptions can be partially overlapped. The design has been implemented on EP20k300EBC652-l device (Ateral).
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Received: 17 June 2003
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2005, Vol. 27 
