Abstract：Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitioning for parallel simulations has been shown to be vital for achieving higher simulation throughput. This paper presents the design and implementation of a new partitioning algorithm based on a multilevel heuristic, also presents the speed up of applying this to a real hardware parallel simulation system Discovery. This algorithm attempts to balance load and reduce the whole simulation network communication to improve performance. The experimental results obtained from the benchmarks indicate that this algorithm yields better partitions than other partitioning algorithms for better simulation performance.
吕蒙, 付宇卓. 一种新的应用于并行数字仿真的电路划分算法[J]. 电子与信息学报, 2007, 29(4): 1009-1012 .
Lv Meng , Fu Yu-Zhuo. A Novel Arithmetic of Circuits Partition Used in Parallel Digital Simulation. , 2007, 29(4): 1009-1012 .
2007, Vol. 29 
