Abstract:Memory Cell is a basic and important macro block of SRAM. It has played a positive role in improving performance and reliability, lowering cost and power consumption. In this paper a new physical alpha-power law MOSEFT model is used to establish power and delay model related with SRAM memory cell. Adopting those performance models, memory cell area model and reliability analysis, a new memory cell structure optimization method is proposed. Experimental result shows SRAM power, access time and area are reduced by adopting this method, and computed performance parameter varies less than 10% compares with simulation result. Experiment results indicate the effectiveness and validity of the performance model and optimization method.