The Research of Area-Efficiency for the Routing Channel Distribution in FPGAs
Xu Xin-min①; Wang Qian①; Yan Xiao-lang②
①Institute of Electronic Circuit and Information System, Zhejiang University, Hangzhou 310027, China; ②Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
Abstract：The effect of track distribution on chip area is investigated in this paper. Several typical distributions in math (Gaussian, Sine and Trigonal) are introduced to realize FPGAs architectures with routing channel width varying randomly on software platform. These various kinds of FPGA architecture are made comparison to the traditional FPGA with uniform routing channel width. The key results are that the non-uniform routing architectures educed from the introduction of math’s distribution have a better area efficient than the uniform ones without sacrificing the circuit speed. And the trend of routing channel width transformation is that in the center of the chip is the peak point, and from the center to the edges the channel width becomes narrow gradually.
徐新民; 王 倩; 严晓浪. FPGA布线通道分布对面积效率的影响研究[J]. 电子与信息学报, 2006, 28(10): 1959-1962 .
Xu Xin-min①; Wang Qian①; Yan Xiao-lang②. The Research of Area-Efficiency for the Routing Channel Distribution in FPGAs. , 2006, 28(10): 1959-1962 .
2006, Vol. 28 
