Abstract：A reconfigurable and fast architecture over Galois field GF (2m )(1＜m≤M) is presented based on the improved serial multiplier. The value m, of the irreducible polynomial degree, can changed by adding a set of configuring signals and logic circuits, which results in that the multiplier architecture is reconfigurable and programmable without changing the hardware. The proposed multiplier architecture has high order of flexibility and low hardware complexity. Compared with the traditional serial multiplier, it can obtain twice speed-up. It suits high-security cryptographic applications with variable finite fields and low complexity requirements.
2006, Vol. 28 
