Study on the Effect of Upset and Recovery for SRAM Under the Varying Parameters of PMOS Transistor
ZHANG Jingbo①② YANG Zhiping① PENG Chunyu① DING Penghui① WU Xiulong①
①(School of Electronics and Information Engineering, Anhui University, Hefei 230601, China) ②(Industry Development and Promotion Center of Ministry of Industry and Information Technology, Beijing 100804, China)
Abstract：Based on Synopsys TCAD 3-D device simulation, the effects of PMOS transistor process parameters on the upset and recovery effect of Static Random Access Memory (SRAM) memory cell are studied in a 65-nm bulk CMOS technology, mainly by changing the three process parameters. The simulation results show that reducing the doping concentration of deep-P+-well, N-well and threshold doping concentration in PMOS transistor can decrease the Linear Energy Transfer (LET) value of the upset and recovery. By reducing the doping concentration of deep-P+-well and N-well in PMOS transistor, the time of the upset and recovery increases. The conclusion of this paper is helpful to optimize the design of Static Random Access Memory cell mitigating Single-Event Effect (SEE), and can gives a great guidance for the anti-radiation integrated circuit under bulk CMOS process.
张景波,杨志平,彭春雨,丁朋辉,吴秀龙. PMOS晶体管工艺参数变化对SRAM单元翻转恢复效应影响的研究[J]. 电子与信息学报, 2017, 39(11): 2755-2762.
ZHANG Jingbo, YANG Zhiping, PENG Chunyu, DING Penghui, WU Xiulong. Study on the Effect of Upset and Recovery for SRAM Under the Varying Parameters of PMOS Transistor. JEIT, 2017, 39(11): 2755-2762.
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