Abstract：A novel C-element connect method is proposed. The gate of P-type/N-type transistor is modified from the top/bottom of conventional C-element to connect to output, which takes advantage of the transistor,s own feedback mechanism to form a feedback path to achieve the self-recovery function. Therefore, the dynamic performance and hardware overhead are significant reduced. The node-enhanced C-element is used as the output stage circuit and optimized, making the circuit more resistant to single event upset. Based on the above description, a novel soft error-tolerant latch is proposed. Due to the only transmission gate in the shortest route between input and output, the delay in signal transmission is reduced. The critical charge can be further enhanced by using feedback comparison mechanism. Compared with latches in literature at 22 nm CMOS process, the results show that the proposed latch performs greater in reliability and the power delay products improvement of proposed latch achieves 26.74%~97.50%.
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