Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop
TIAN Yuze①② WANG Yu② DAI Haishan③ FANG Hua③ LIU Wenqing②
①(School of Environmental Science and Optoelectronic Technology, University of Science and Technology of China, Hefei 230027, China) ②(Key Laboratory of Environment Optics and Technology, Anhui Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Hefei 230031, China) ③(Shanghai Satellite Engineering Research Institute, Shanghai 200240, China)
Abstract：Under the condition of working in sun-synchronous orbit, the error correction strategy is put forward due to the error caused by the communication error. According to the complementary error characteristics between satellite clock and local clock, a Digital Phase Locked Loop (DPLL) is designed, which is applied to the low frequency input signal and the large frequency multiplication factor. The local clock tracks the satellite clock pulse phase fluctuations and eliminates the accumulate error constantly. The complete design is developed with Field Programmable Gate Array (FPGA) devices and the detailed theoretical analysis and experimental results are presented. Experiments show that the design of the clock source can correct the abnormal flip or lose of second pulse and jump or lose of broadcast time package constantly. It can enter the lock state in 5 input clock cycles, and the cumulative error is less than 100 μs. It can be used as the local clock source of satellite borne equipment.
田禹泽, 王煜,代海山,方华,刘文清. 基于数字锁相环的星载光谱仪本地时钟源设计[J]. 电子与信息学报, 2017, 39(10): 2397-2403.
TIAN Yuze, WANG Yu, DAI Haishan, FANG Hua, LIU Wenqing. Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop. JEIT, 2017, 39(10): 2397-2403.
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