This paper presents an effective method based on transfer function to predict the jitter performance of self biased PLL due to power supply noise. The supply noise sensitivity of replica biased regulator of PLL is derived from small signal analysis. The analysis shows that there exist tradeoffs between the closed-loop bandwidth and supply noise sensitivity of regulator. As an example, the supply noise performance of one specific self biased PLL which is used as a clock generator in PI based CDR is analyzed. The comparison between transient simulation method and the proposed method is made. The results show that the proposed method can predict the value of period jitter with considerable accuracy. It can also give guidelines on how to further improve the noise performance of SBPLL.
MANEATIS J G. Low-jitter process-independent DLL and PLL based on self-biased techniques[J]. IEEE Journal of Solid-State Circuits, 1996, 31(11): 1723-1732. doi: 10.1109/ JSSC.1996.542317.
[2]
MANEATIS J G, KIM J, MCCLATCHIE I, et al. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL[J]. IEEE Journal of Solid-State Circuits, 2003, 38(11): 1795-1803. doi: 10.1109/JSSC.2003.818298.
[3]
GANG Yan, CHENXIAO Ren, ZHENDONG Guo, et al. A self-biased PLL with current-mode filter for clock generation[C]. ISSCC 2005 IEEE International Digest of Technical Papers Solid-State Circuits Conference, San Francisco, CA, USA, 2005: 420-421 Vol. 421.
[4]
GHOSH P P, and XIAO E. A 2.5 GHz radiation hard fully self-biased PLL using 0.25 um SOS-CMOS technology[C]. 2009 IEEE International Conference on IC Design and Technology, Austin, TX, USA, 2009: 121-124.
[5]
VISWANATHAN B, VISWAM V, Vettickatt J J, et al. 4 GHz 130 nm low voltage PLL based on self biased technique[C]. The 23rd International Conference on VLSI Design, Bangalore, India, 2010: 330-334.
[6]
YOGESH M, DIETL M, SAREEN P, et al. A low power, self-biased, bandwidth tracking semi-digital PLL design[C]. 2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA), Kuala Lumpur, Malaysia, 2012: 135-140.
[7]
GAO X, KLUMPERINK E A M, GERAEDTS P F J, et al. Jitter analysis and a benchmarking figure-of-merit for phase-locked loops[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2009, 56(2): 117-121. doi: 10.1109 /TCSII.2008.2010189.
[8]
ZHAO B, and YANG H. Supply-noise interactions among submodules inside a charge-pump PLL[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015, 23(4): 771-775. doi: 10.1109/TVLSI.2014. 2317710.
[9]
BIDAJ K, BEGUERET J B, HOUDALI N, et al. Time-domain PLL modeling and RJ/DJ jitter decomposition[C]. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016: 185-188.
[10]
BONDALAPATI P, and NAMGOONG W. Nonlinear analysis of bang-bang digital PLL with accumulative noise using Markov chains[C]. 2016 Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS), Waco, TX, USA, 2016: 1-4.
[11]
VASILYEV G S, KUZICHKIN O R, KURILOV I A, et al. Analysis of noise properties of hybrid frequency synthesizer with autocompensating phase noise of DDS and PLL[C]. 2016 International Siberian Conference on Control and Communications (SIBCON), Shell, Singapore, 2016 : 1-6.
[12]
ARAKALI A, GONDI S, and HANUMOLU P K. Low-power supply-regulation techniques for ring oscillators in phase-locked loops using a split-tuned architecture[J]. IEEE Journal of Solid-State Circuits, 2009, 44(8): 2169-2181. doi: 10.1109/JSSC.2009.2022916.
[13]
ZHU K, SAXENA V, WU X, et al. Design analysis of a 12.5 GHz PLL in 130 nm SiGe BiCMOS process[C]. 2015 IEEE Workshop on Microelectronics and Electron Devices (WMED), Boise, ID, USA, 2015: 1-4.
[14]
LIU L and POKHAREL R. Compact modeling of phase- locked loop frequency synthesizer for transient phase noise and jitter simulation[J]. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 2016, 35(1): 166-170. doi: 10.1109/TCAD.2015.2472018.
[15]
GARDNER F. Charge-pump phase-lock loops[J]. IEEE Transactions on Communications, 1980, 28(11): 1849-1858. doi: 10.1109/TCOM.1980.1094619.
[16]
CASPER B and O'MAHONY F. Clocking analysis, implementation and measurement techniques for high-speed data links—a tutorial[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2009, 56(1): 17-39. doi: 10.1109/ TCSI.2008.931647.
