In order to improve the BER performance of MLC NAND Flash, this paper presents a shortened polarization-based optimized codes for MLC NAND Flash. Optimized shortened codes are obtained by optimizing shortened pattern. Firstly, basic shortened pattern is obtained by bit reversal reordering, and then the freeze bits are selected with a lower channel capacity to constitute optimized shortened pattern, the resulting punctered bits are all frozen bits, this method can significantly improve the error correction performance. Meanwhile, according to the error asymmetry of MLC unit, unequal error protection is used for the LSB and MSB. Simulation results show that the performance of the optimized shortened codes is better than LDPC and basic shortened polar code about 3.72~5.89 dB and 1.47~3.49 dB gain at the frame error rate of 10-3; compared to the same rate based optimized shortened codes, the new ECC program obtains gain about 0.25 dB .
郭锐,王美洁,王杰. 基于缩短极化码的MLC NAND Flash差错控制技术研究[J]. 电子与信息学报, 2017, 39(7): 1658-1665.
GUO Rui, WANG Meijie, WANG Jie. Research on the MLC Nand Flash Error Control Technology Based on Polar Codes. JEIT, 2017, 39(7): 1658-1665.
ASLAM C A, GUAN Y L, and CAI K. Dynamic write-level and read-level signal design for MLC NAND flash memory[C]. 2014 9th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP), Manchester, 2014: 336-341. doi: 10.1109/CSNDSP.2014. 6923850.
[2]
SUN H, ZHAO W, LU M, et al. Exploiting intracell bit-error characteristics to improve min-sum LDPC decoding for MLC NAND flash-based storage in mobile device[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(8): 2654-2664. doi: 10.1109/TVLSI.2016.2535224.
[3]
ASLAM C A, YONG L G, and CAI K. Optimal read and write signal design for multi-level-cell NAND flash memory[J]. IEEE Transactions on Communications, 2016, 64(4): 1613-1623. doi: 10.1109/TCOMM.2016.2533498.
[4]
HO Kinchu, CHEN Chihlung, and CHANG Hsiechia. A 520k (18900, 17010) array dispersion LDPC decoder architectures for NAND flash memory[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(4): 1293-1304. doi: 10.1109/TVLSI.2015.2464092.
[5]
KIM Daesung and HA Jeongseok. Serial quasi-primitive BC- BCH codes for NAND flash memories[C]. 2016 IEEE International Conference on Communications (ICC), Beijing, 2016: 1-6. doi: 10.1109/ICC.2016.7510725.
[6]
ARIKAN E. Channel polarization: A method for constructing capacity-achieving codes for symmetric binary- input memory less channels[J]. IEEE Transactions on Information Theory, 2009, 55(7): 3051-3073. doi: 10.1109/ TIT.2009. 2021379.
[7]
ESLAMI A and PISHRO N. A practical approach to polar codes[C]. 2011 IEEE International Symposium on Information Theory Proceedings (ISIT), St. Petersburg, 2011: 16-20. doi: 10.1109/ISIT.2011.6033837.
[8]
SHIN D M, LIM S C, and YANG K. Design of length- compatible polar codes based on the reduction of polarizing matrices[J]. IEEE Transactions on Communications, 2013, 61(7): 2593-2599. doi: 10.1109/TCOMM.2013.052013. 120543.
[9]
LI Y, ALHUSSIEN H, HARATSCH E F, et al. A study of polar codes for MLC NAND flash memories[C]. 2015 International Conference on Computing, Networking and Communications (ICNC), Garden Grove, CA, 2015: 608-612. doi: 10. 1109/ICCNC.2015.7069414.
[10]
LIU Y, LIU Huaida, JIN Pingui, et al. An adaptive ECC scheme for dynamic protection of NAND flash memories[C]. 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), South Brisbane, QLD, 2015: 1052-1055. doi: 10.1109/ICASSP.2015.7178130.
[11]
NIU K, CHEN K, and LIN J R. Beyond turbo codes: Rate- compatible punctured polar codes[C]. 2013 IEEE International Conference on Communications (ICC), Budapest, 2013: 3423-3427. doi: 10.1109/ICC.2013.6655078.
[12]
TARANALLI V, UCHIKAWA H, and SIEGEL P H. Channel models for multi-level cell flash memories based on empirical error analysis[J]. IEEE Transactions on Communications, 2016, 64(8): 3169-3181. doi: 10.1109/TCOMM.2016.2584602.
[13]
LIU Yumin, LIU Huaiting, CHEN Minghan, et al. Byte- reconfigurable LDPC codec design with application to high- performance ECC of NAND flash memory systems[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2015, 62(7): 1794-1804. doi: 10.1109/TCSI.2015.2423798.
[14]
MACKAY J C. Good error-correcting codes based on very sparse matrices[J]. IEEE Transactions on Information Theory, 1999, 45(2): 399-431. doi: 10.1109/18.748992.
[15]
TAI I and VARDY A. How to construct polar codes[J]. IEEE Transactions on Information Theory, 2013, 59(10): 6562-6582. doi: 10.1109/TIT.2013.2272694.
