There are increasing interests in hardware support for decimal arithmetic due to the demand of high accuracy computation in commercial computing, financial analysis, and other applications. New specifications for decimal floating-point arithmetic have been added to the revised IEEE 754-2008 standard. In this paper, the algorithm and architecture of decimal addition is studied comprehensively. A decimal adder is designed by using the parallel-prefix/carry-select architecture. The parallel-prefix unit is used to optimize the decimal carry select adder. The decimal adder has been realized by Verilog HDL and simulated with ModelSim. The synthesis results of this design by Design Compiler is also given and analyzed under Nangate Open Cell 45nm library. The results show that the delay performance of the proposed circuit can be improved by up to 12.3%.
崔晓平,王书敏,刘伟强,董文雯. 条件推测性十进制加法器的优化设计[J]. 电子与信息学报, 2016, 38(10): 2689-2694.
CUI Xiaoping, WANG Shumin, LIU Weiqiang, DONG Wenwen. Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen. JEIT, 2016, 38(10): 2689-2694.
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