An Efficient LDPC Encoder Scheme with Low-power Low-parallel
YAN Wei XUE Changbin
(National Space Science Center, Chinese Academy of Sciences, Beijing 100190, China)
(Key Laboratory of Integrated Avionics and Information Technology for Complex Aerospace Systems, Chinese Academy of Sciences, Beijing 100190, China)
Low-density parity-check code is the one of error-correction codes most approaching Shannon limit, which is adopted as a standard for channel coding by many international communication standard organizations. CCSDS recommends LDPC as channel coding scheme in near earth space and deep space communication. An efficient LDPC coding scheme with low power and low parallel is presented in this paper. By filling “0” and changing the cyclic-matrix structure, the proposed scheme implements a low parallel coding for the LDPC, which is recommended by CCSDS, and of which the size of submatrix of check matrices is odd. By analyzing the coding process, the valid bit “1” among input information bits is coded only, and it decreases obviously the code power. The encoder architecture for 7/8 LDPC is implemented in FPGA. The result shows that encoder achieves a high encoding speed approaching low parallel encoder scheme and a much lower encoding power while increases few hardware overhead.
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