Propagation Mechanism of Single Event Transient and Soft Error Rate Analysis Method Based on Four-value Pulse Parameters Model
LI Yue①② CAI Gang① LI Tianwen① YANG Haigang①
①(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China) ②(University of the Chinese Academy of Sciences, Beijing 100049, China)
With the shrinking of feature size, soft errors due to Single Event Transient (SET) effect become the main reliability threat for aerospace deep sub-micron VLSI circuits, and the generation and propagation of SET pulse is also a hot issue in the study of soft error. Results of SET pulse propagation on logic chains show that the difference of rise and fall time of SET pulse can make the width of output pulse widened or lessened. The width and amplitude of SET pulse can determine whether it is electrically masked out. A four-value pulse parameters model is proposed to accurately characterize the shape of SET pulse, and then the LUT-based technique is combined with experiential equations to model the transmission process of SET. The proposed four-value pulse parameters model can model the effect of broadening or attenuation of SET pulse, and it has calculation precision improvement of 2.4% compared with single parameter model. This paper applies the graph-based error propagation probability analytic algorithm to estimate the logical masking in pulse propagation. The experimental results on ISCAS’89 and ISCAS’85 circuits show that the average deviation of this method and HSPICE simulation method is 4.12% and the calculation speed is 10000 times. This method can be used to analyze quickly the soft error rate of large scale integrated circuits.
李悦,蔡刚,李天文,杨海钢. 基于四值脉冲参数模型的单粒子瞬态传播机理与软错误率分析方法[J]. 电子与信息学报, 2016, 38(8): 2113-2121.
LI Yue, CAI Gang, LI Tianwen, YANG Haigang. Propagation Mechanism of Single Event Transient and Soft Error Rate Analysis Method Based on Four-value Pulse Parameters Model. JEIT, 2016, 38(8): 2113-2121.
WANG Zhen, LI Fang, and LU Fangfang. Survey on circuit soft error rate evaluation[J]. Journal of Shanghai University of Electric Power, 2015, 31(4): 369-375. doi: 10.3969/j.issn. 1006-4729.2015.04.013.
YAN Aibin, LIANG Huaguo, HUANG Zhengfeng, et al. Fault probability based SER analysis for combinational logic circuits[J]. Journal of Electronic Measurement and Instrumentation, 2015, 29(3): 343-351. doi: 10.13382/j.jemi. 2015.03.005.
[3]
HENKEL J, BAUER L, DUTT N, et al. Reliable on-chip systems in the nano-era: Lessons learnt and future trends[C]. 50th ACM/EDAC/IEEE Design Automation Conference, Austin, TX, USA, 2013: 1-10. doi: 10.1145/2463209.2488857.
CAI Shuo, KUANG Jishun, ZHANG Liang, et al. Reliability estimation for soft error of sequential circuit based on error propagation probability matrix[J]. Chinese Journal of Computer, 2015, 38(5): 923-931. doi: 10.3724/SP.J.1016. 2015.00923.
[6]
MAHATME N N, GASPARD N J, ASSIS T, et al. Impact of technology scaling on the combinational logic soft error rate[C]. IEEE International Reliability Physics Symposium, Waikoloa, HI, USA, 2014: 5F.2.1-5F.2.6. doi: 10.1109/IRPS. 2014. 6861093.
[7]
MOHANRAM K. Simulation of transients caused by single- event upsets in combinational logic[C]. IEEE International Test Conference, Austin, TX, USA, 2005: 973-981. doi: 10.1109/TEST. 2005.1584063.
[8]
WANG F, XIE Y, RAJARAMANT R, et al. Soft error rate analysis for combinational logic using an accurate electrical masking model[C]. 20th International Conference on VLSI Design, Bangalore, India, 2007: 165-170. doi: 10.1109/ VLSID.2007. 145.
[9]
MANSOUR W and VELAZCO R. An automated SEU fault-injection method and tool for HDL-based designs[J]. IEEE Transactions on Nuclear Science, 2013, 60(4): 2728-2733. doi: 10.1109/TNS.2013.2267097.
[10]
ENTRENA L, VALDERAS M G, CARDENAL R F, et al. Soft error sensitivity evaluation of mi-croprocessors by multilevel emulation-based fault injection[J]. IEEE Transactions on Computers, 2012, 61(3): 313-322. doi: 10.1109/TC.2010.262.
[11]
ZHANG Ming and SHANBHAG N R. Soft-error-rate- analysis (SERA) methodology[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(10): 2140-2155. doi: 10.1109/ICCAD.2004.1382553.
[12]
RAJARAMANT R, KIM J S, VIJAYKRISHNAN N, et al. SEAT-LA: a soft error analysis tool for combinational logic[C]. Proceedings of the 19th International Conference on VLSI Design, Hyderabad, India, 2006: 499-502. doi: 10.1109/ VLSID.2006.143.
[13]
RAO R R, CHOPRA K, BLAAUW D T, et al. Computing the soft error rate of a combinational logic circuit using parameterized descriptors[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(3): 468-479. doi: 10.1109/TCAD.2007.891036.
[14]
ZIVANOV N M and MARCULESCU D. Circuit reliability analysis using symbolic techniques[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(12): 2638-2649. doi: 10.1109/TCAD.2006.882592.
[15]
ZIVANOV N M and MARCULESCU D. Modeling and optimization for soft-error reliability of sequential circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(5): 803-816. doi: 10.1109/ TCAD.2008.917591.
[16]
ASADI H, TAHOORI M B, FAZELI M, et al. Efficient algorithms to accurately compute derating factors of digital circuits[J]. Microelectronics Reliability, 2012, 52: 1215-1226.
[17]
HAMAD G, HASAN S, MOHAMED O, et al. New insights into the single event transient propagation through static and TSPC logic[J]. IEEE Transactions on Nuclear Science, 2014, 61(4): 1618-1627. doi: 10.1109/TNS.2014.2305434.
[18]
ARTOLA L, GAILLARDIN M, HUBERT G, et al. Modeling single event transients in advanced devices and ICs[J]. IEEE Transactions on Nuclear Science, 2015, 62(4): 1528-1539. doi: 10.1109/TNS.2015.2432271.
[19]
SHIVAKUMAR P, KISTLER M, KECKLER S W, et al. Modeling the effect of technology trends on the soft error rate of combinational logic[C]. International Conference on Dependable Systems and Networks, Bethesda, MD, USA, 2002: 389-398. doi: 10.1109/DSN.2002.1028924.
[20]
OMANA M, PAPASSO G, ROSSI D, et al. A model for transient fault propagation in combinational logic[C]. Proceedings of the 9th IEEE International On-Line Testing Symposium, Greece, 2003: 111-115. doi: 10.1109/ICECS. 2015.7440265.
[21]
FIROUZI F, KIAMEHR S, MONSHIZADEH P, et al. A model for transient fault propagation considering glitch amplitude and rise-fall time mismatch[C]. 2nd Asia Symposium on Quality Electronic Design, Penang, Malaysia, 2010: 89-92. doi: 10.1109/ASQED.2010.5548223.
[22]
RAO R R, CHOPRA K, BLAAUW D, et al. An efficient static algorithm for computing the soft error rates of combinational circuits[C]. Design, Automation and Test in Europe, Munich, Germany, 2006, 1: 1-6. doi: 10.1109/DATE. 2006. 244060.
[23]
ZHANG B, WANG W S, and ORSHANSKY M. FASER: fast analysis of soft error susceptibility for cell-based designs[C]. Proceedings of the 7th International Symposium on Quality Electronic Design, San Jose, CA, USA, 2006: 755-760. doi: 10.1109/ISQED.2006.64.
