Efficient Encoding Architecture for LDPC Code Based on DVB-S2 Standard
LAN Yazhu①② YANG Haigang① LIN Yu①
①(System of Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China) ②(University of Chinese Academy of Sciences, Beijing 100049, China)
For DVB-S2 standard LDPC code, to achieve an efficient encoding architecture based on FPGA, a fast pipeline parallel and recursive encoding algorithm is proposed which can significantly improve encoding speed and improve the encoding data rate of information throughput. At the same time, the parallel shift operation and parallel XOR processing structure is introduced to calculate code intermediate variable. It can effectively improve the encoding parallel degree and reduce the occupancy volume of storage resources. In addition, according to dynamic adaptive encoding, the storage structure and effective reuse of data storage unit and the RAM address generator are optimized. In this case, the utilization of FPGA resources is further improved. The experiment based on Stratix IV series FPGA for DVB-S2 standard LDPC code, shows that the proposed method can achieve system clock frequency of 126.17 MHz and encoding data rate of information throughput of more than 20 Gbps.
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