Jiang Zheng-hong①② Lin Yu① Huang Zhi-hong① Yang Li-qun①② Yang Hai-gang①
①(System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China) ②(University of Chinese Academy of Sciences, Beijing 100049, China)
Exploring a new logic element of Field Programmable Gate Array (FPGA) is always a key field in FPGAs’ research, while And-Inverter Cones (AIC) is the most promising one. Implementing a highly-efficient and highly-flexible mapping tool is also an important part of exploring new FPGA architecture. In this paper, a new mapper for AIC-based FPGA is implemented. Compared with an existing mapper, the new mapper has much higher flexibility, and supports adjustments of AICs’ architectural parameters to assit the design space exploration of AIC. Meanwhile, the new mapper provides area results 33%~36% better than the original mapper.
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