Design of Dynamic Adaptive LDPC Decoder Based on FPGA
Lan Ya-zhu①② Yang Hai-gang① Lin Yu①
①(System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China) ②(University of Chinese Academy of Sciences, Beijing 100049, China)
Faced with the complex environment of deep space communication, the adaptive capacity can have an impact on the ability of the Low Density Parity Check (LDPC) code decoder to maintain long-term stability. This paper proposes a design method of dynamic adaptive LDPC code decoder. Through the IP-based design of each function module, the design method of dynamic adaptive can be mapped to each function module in DVB-S2 LDPC code decoder. The verification results based on the Stratix IV FPGA show the dynamic adaptive LDPC code decoder not only can decode under the different code length and code rate, but also can decode under the different decoding performance. Meanwhile, the single-channel decoder can ensure the information throughput to reach to 40.9~71.7 Mbps.
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