Abstract：Reconfigurable Low-Density Parity-Check (LDPC) codes decoders adapted to multiple standards attracte more and more attentions in thesatellite application. However, due to the memory resource is limited on the satellite and sensitive to the space radiation effect, the conventional reconfigurable decoders are difficult to be applied to on-board processing for their high memory requirements. This paper presents a novel reconfigurable decoder with layered pipelined architecture to achieve high throughput and realizes low complexity by combining the structural characteristics of different LDPC codes. The memory size is reduced by simplifying the storage of the channel intrinsic Logarithm Likelihood Ratio (LLR) messages and the passed messages in the process of iterative decoding. The decoder is fabricated in the TSMC 0.13 μm standard CMOS technology and the result shows that each branch can achieve a throughput up to 1.5 Gbps with 7.8 mm2 core area occupancy and can save 40% storage resource at most.
2014, Vol. 36 
