①(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China) ②(Graduate University, Chinese Academy of Sciences, Beijing 100049, China)
Abstract:Through Silicon Via (TSV) is the key technology for vertical interconnections in 3D ICs, with insulator short and bump open being the two major types of TSV defects. In this paper, a TSV defect model is presented and the relationships between the linear oxide resistance/bump resistance and the TSV dimension are discussed. Based on the model, a method is proposed for detecting the voltage of the defects’ resistance. To verify the proposed method, a self-test circuit which can detect both types of defects is designed, and it can be cascaded to achieve auto-recovery on chip. Then, the area overhead is analyzed and the results show that self-test/recovery circuits will occupy lower percentage of total chip area as CMOS/TSV fabrication technology scales down or as TSV array size increases.
余乐, 杨海钢, 谢元禄, 张甲, 张春红, 韦援丰. 三维集成电路中硅通孔缺陷建模及自测试/修复方法研究[J]. 电子与信息学报, 2012, 34(9): 2247-2253.
Yu Le, Yang Hai-Gang, Xie Yuan-Lu, Zhang Jia, Zhang Chun-Hong, Wei Yuan-Feng. A 3D IC Self-test and Recovery Method Based on Through Silicon Via Defect Modeling. , 2012, 34(9): 2247-2253.