An Efficient Parallel Architecture for One-bit Transform Based Motion Estimation
Chen Yun-bi① Guo Li① Li Zheng-dong② Chi Ling-hong①
①(Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China) ②(Staff room of Electronic and Technology, Chongqing Communication College, Chongqing 400035, China)
Abstract：In order to meet the processing requirements of portable real-time full HD video compression, this paper proposes a novel macroblock-level parallel architecture based on 1-D source pixels based linear array, which overcomes the problem of massive amount of resources and large delay caused by 2-D arrays used in literatures. The proposed architecture is easy to extend and area-economical. Furthermore, towards the system bottlenecks, systolic cell and data memory organization, optimized structure are presented. Compared with the traditional architecture, the proposed architecture can achieve the improvements of speed and area at the same time. FPGA implementation results show that, LUTs is reduced by 43%, DFFs is reduced by 25%, BRAMs is reduced by 75%, and performance is increased by 32%.
2011, Vol. 33 
