An Improved Digital Decimation Filter for Sigma-Delta ADC
Hao Zhi-gang①②; Yang Hai-gang①; Zhang Chong①②; Wu Qi-song①②; Yin Tao①
①Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China; ②Graduate University of Chinese Academy of Sciences, Beijing 100049, China
摘要 数字滤波器在sigma-delta ADC芯片中占据了大部分芯片面积,该文提出了一种数字滤波器结构,这种结构滤波器采用一个控制单元和一个加法器取代了Hogenauer结构滤波器中差分器的多个加法器,从而减小数字电路的面积。一个采用这种结构的4阶的数字滤波器在CYCLONE II FPGA芯片中被实现,耗费的硬件资源比Hogenauer结构的滤波器减少近29%。
Abstract:Usually in a sigma-delta ADC, the digital filter takes most of the chip area. In this paper, a novel digital filer topology is proposed, in which the differentiator is constructed with a control unit and an adder instead of the multiple of adders in the Hogenauer structure filter, so that the digital circuit area should be reduced. A fourth order digital filter employing such topology is implemented in a Cyclone-II FPGA, and costs chip resources 29 percent less than in a Hogenauer structure.