Abstract：In this paper a synthesis for low power circuits is studied and an adiabatic ratioiess dynamic memory circuit is expressed quantitatively in accordance with the theory of three essential circuit elements. Then many adiabatic ratioiess dynamic flip-flops are composed of two adiabatic ratioiess dynamic latches, for example D or T’ flip-flop of 6 MOS transistors and D flip-flop with AND-NOR-inputs of 9 MOS transistors, in which there is no phenomenon of information disappearing rapidly after receiving one in capacitors. On the basis of above theory, this paper presents a synthesis for adiabatic synchronous sequential circuits, and designs an adiabatic 5421BCD decimal counter circuit of 32 MOS transistors which consumes lower power than that of an adiabatic PAL-2N 4-bit binary counter. Above theory is vertified by computer simulation.
2002, Vol. 24 
